1. Field of the Invention
The invention relates in general to the design of integrated circuits and more particularly, to the use of modes at different levels of abstraction during the design of integrated circuits.
2. Description of the Related Art
Modern circuit design has evolved into a specialized field often referred to as electronic design automation in which computers and computer aided design (CAD) techniques are used to automate the integrated circuit (IC) design process. An IC design process typically begins with an engineer specifying the input/output signals, functionality and performance characteristics of a hardware circuit to be fabricated. In the past the design of integrated circuits often involved creation of a low level Register Transfer Level (RTL) model of an IC device, which was used as an input to an automated digital synthesis tool. More particularly, an RTL model specifies storage elements (e.g. latches, flip-flops, memory words) that accept input logic states and hold them as directed by timing signals. The timing signals may be clock edges, clock phases or reset, for example. Transfer refers to input-to-register, register-to-register and register-to-output equations and/or transformations. Although there may be a range of abstractions for RTL equation and transformation notations, RTL provides cycle-by-cycle state-by-state correspondence with gate-level design. However all of the detailed timing and synchronization information in RTL models often causes them to simulate relatively slowly. Unfortunately, this can make them not well suited to running simulations with real inputs.
One alternative is to accelerate testing of a design by running it on a hardware emulator. Often although an emulator runs fast enough for testing the core routines of a circuit; it still may be too slow to test software designed to run on the IC design. Another problem with using an emulator is that one must have the IC design at a state of development where it is completely specified, and ready to be fabricated into hardware in order to run the design on an emulator. Since emulators are very expensive, some companies just skip the emulation step and fabricate the actual chip, and test the software at full hardware speed. In view of the costs of emulation and the time required for more thorough simulation, they take the risk that the resulting chip will function adequately even though testing, particularly software testing, has been cut short. If there are hardware bugs that are not too severe, then a software work around may suffice to make the IC useable. If there are bugs that are too severe to work around using software, then the chip hardware may have to be changed, which typically requires a re-design and fabrication of a new chip at significant cost in time and money.
More recently, Transaction Level Model (TLM) based design methodology has been proposed. A system architecture model is produced that describes a product specification or critical system parameters. The system architecture model is refined into a transaction level model (TLM). The transaction level model is used in the development of RTL models suitable for synthesis and in parallel development of software.
While earlier approaches to design of integrated circuits generally have been acceptable, there have been shortcomings with their use. For example, there has been a need for a techniques to improve coordination of hardware and software development during IC design. The present invention meets this need.